F
faye_hongdou
Guest
Code:modul mix_nco (cr_cntr_freq, d_en, s_out, c_out, clk, reset);output [11:0] s_out, c_out;
input [15:0] cr_cntr_freq;
input d_en, clk, reset;wire [15:0] cr_in;
wire [11:0] a_out;
reg [15:0] cr_out;
wire [11:0] s_out_l, c_out_l;
reg [11:0] s_out, c_out;tildele cr_in = cr_cntr_freq cr_out;
tildele a_out = cr_out [15:4] / /-adressen er den høye 12 biter av cr_outalltid @ (posedge clk eller posedge reset)
begynne
if (reset) cr_out <= # 1 1'b0;
else if (d_en) cr_out <= # 1 cr_in;
slutttabeller table_1 (a_out, s_out_l, c_out_l);alltid @ (posedge clk eller posedge reset)
if (reset)
begynne
c_out <= # 1 0;
s_out <= # 1 0;
slutt
ellers
begynne
c_out <= # 1 c_out_l;
s_out <= # 1 s_out_l;
sluttendmodule
input [15:0] cr_cntr_freq;
input d_en, clk, reset;wire [15:0] cr_in;
wire [11:0] a_out;
reg [15:0] cr_out;
wire [11:0] s_out_l, c_out_l;
reg [11:0] s_out, c_out;tildele cr_in = cr_cntr_freq cr_out;
tildele a_out = cr_out [15:4] / /-adressen er den høye 12 biter av cr_outalltid @ (posedge clk eller posedge reset)
begynne
if (reset) cr_out <= # 1 1'b0;
else if (d_en) cr_out <= # 1 cr_in;
slutttabeller table_1 (a_out, s_out_l, c_out_l);alltid @ (posedge clk eller posedge reset)
if (reset)
begynne
c_out <= # 1 0;
s_out <= # 1 0;
slutt
ellers
begynne
c_out <= # 1 c_out_l;
s_out <= # 1 s_out_l;
sluttendmodule