L
lekhoi
Guest
Hi guys!
Jeg hjelper en kode for mus grensesnitt, men det fortsatt ikke fungerer.Kan noen hjelpe meg å sortere det ut?
`tidsskalaen 1ns / 1ps
////////////////////////////////////////////////// //////////////////////////////
/ / Firma:
/ / Engineer:
/ /
/ / Create Date: 19:54:03 04/20/06
/ / Design Navn:
/ / Module Name: dgfd
/ / Project Name:
/ / Målenheten:
/ / Tool versjoner:
/ / Description:
/ /
/ / Avhengigheter:
/ /
/ / Revisjon:
/ / Versjon 0.01 - Arkiv Opprettet
/ / Additional Comments:
/ /
////////////////////////////////////////////////// //////////////////////////////
`resetall
`tidsskala 1ns/100ps
`definere TOTAL_BITS 33 / / Antall bits i en full pakkemodul ps2_mouse_interface (
CLK,
reset,
ps2_clk,
ps2_data,
left_button,
right_button,
x_increment,
y_increment,
data_ready, / / rx_read_o
lese, / / rx_read_ack_i
error_no_ack
);
/ / Parameters
/ / Tidtakeren Verdien kan bli opp til (2 ^ bits) inkluderende.
parameter WATCHDOG_TIMER_VALUE_PP = 19660; / / Antall sys_clks for 400usec.
parameter WATCHDOG_TIMER_BITS_PP = 15; / / Antall bits trengs for tidtaker
parameter DEBOUNCE_TIMER_VALUE_PP = 186; / / Antall sys_clks for debounce
parameter DEBOUNCE_TIMER_BITS_PP = 8; / / Antall bits trengs for tidtakerparameter m1_clk_h = 0;
parameter m1_falling_edge = 1;
parameter m1_falling_wait = 3;
parameter m1_clk_l = 2;
parameter m1_rising_edge = 6;
parameter m1_rising_wait = 4;
parameter m2_reset = 14;
parameter m2_wait = 0;
parameter m2_gather = 1;
parameter m2_verify = 3;
parameter m2_use = 2;
parameter m2_hold_clk_l = 6;
parameter m2_data_low_1 = 4;
parameter m2_data_high_1 = 5;
parameter m2_data_low_2 = 7;
parameter m2_data_high_2 = 8;
parameter m2_data_low_3 = 9;
parameter m2_data_high_3 = 11;
parameter m2_error_no_ack = 15;
parameter m2_await_response = 10;
parameter m3_data_ready = 1;
parameter m3_data_ready_ack = 0;
/ / I / O erklæringer
input clk;
input reset;
Inout ps2_clk;
Inout ps2_data;
output left_button;
output right_button;
output [8:0] x_increment;
output [8:0] y_increment;
output data_ready;
input les;
output error_no_ack;
reg left_button;
reg right_button;
reg [8:0] x_increment;
reg [8:0] y_increment;
reg data_ready;
reg error_no_ack;
/ / Intern signal erklæringer
wire watchdog_timer_done;
wire debounce_timer_done;
wire packet_good;
reg [ `TOTAL_BITS-1: 0] q; / / Shift register
reg [2:0] m1_state;
reg [2:0] m1_next_state;
reg [3:0] m2_state;
reg [3:0] m2_next_state;
reg m3_state;
reg m3_next_state;
reg [5:0] bit_count; / / Bit counter
reg [WATCHDOG_TIMER_BITS_PP-1: 0] watchdog_timer_count;
reg [DEBOUNCE_TIMER_BITS_PP-1: 0] debounce_timer_count;
reg ps2_clk_hi_z; / / Uten tastatur, lik høy Z 1 skyldes pullups.
reg ps2_data_hi_z; / / Uten tastatur, lik høy Z 1 skyldes pullups.
reg clean_clk; / Debounced utgang fra M1, følger ps2_clk.
reg rising_edge; / / Output fra M1 stat maskin.
reg falling_edge; / / Output fra M1 stat maskin.
reg output_strobe; / Latches data data i produksjon registre
//------------------------------------------------ --------------------------
/ / Module kode
tildele ps2_clk = ps2_clk_hi_z? 1'bZ: 1'b0;
tildele ps2_data = ps2_data_hi_z? 1'bZ: 1'b0;
/ / State register
alltid @ (posedge clk)
begin: m1_state_register
if (reset) m1_state <= m1_clk_h;
else m1_state <= m1_next_state;
slutt
/ / State overgang logikk
alltid @ (m1_state
eller ps2_clk
eller debounce_timer_done
eller watchdog_timer_done
)
begin: m1_state_logic
/ / Output signaler standard til denne verdien, hvis ikke endres i en stat tilstand.
clean_clk <= 0;
rising_edge <= 0;
falling_edge <= 0;
case (m1_state)
m1_clk_h:
begynne
clean_clk <= 1;
if (~ ps2_clk) m1_next_state <= m1_falling_edge;
else m1_next_state <= m1_clk_h;
slutt
m1_falling_edge:
begynne
falling_edge <= 1;
m1_next_state <= m1_falling_wait;
slutt
m1_falling_wait:
begynne
if (debounce_timer_done) m1_next_state <= m1_clk_l;
else m1_next_state <= m1_falling_wait;
slutt
m1_clk_l:
begynne
if (ps2_clk) m1_next_state <= m1_rising_edge;
else m1_next_state <= m1_clk_l;
slutt
m1_rising_edge:
begynne
rising_edge <= 1;
m1_next_state <= m1_rising_wait;
slutt
m1_rising_wait:
begynne
clean_clk <= 1;
if (debounce_timer_done) m1_next_state <= m1_clk_h;
else m1_next_state <= m1_rising_wait;
slutt
default: m1_next_state <= m1_clk_h;
endcase
slutt/ / State register
alltid @ (posedge clk)
begin: m2_state_register
if (reset) m2_state <= m2_reset;
else m2_state <= m2_next_state;
slutt
/ / State overgang logikk
alltid @ (m2_state
eller q
eller falling_edge
eller rising_edge
eller watchdog_timer_done
eller bit_count
eller packet_good
eller ps2_data
eller clean_clk
)
begin: m2_state_logic
/ / Output signaler standard til denne verdien, hvis ikke endres i en stat tilstand.
ps2_clk_hi_z <= 1;
ps2_data_hi_z <= 1;
error_no_ack <= 0;
output_strobe <= 0;
case (m2_state)
m2_reset: / / Etter reset, sender kommandoen til musen.
begynne
m2_next_state <= m2_hold_clk_l;
slutt
m2_wait:
begynne
if (falling_edge) m2_next_state <= m2_gather;
else m2_next_state <= m2_wait;
slutt
m2_gather:
begynne
if (watchdog_timer_done & & (bit_count == `TOTAL_BITS))
m2_next_state <= m2_verify;
else if (watchdog_timer_done & & (bit_count < `TOTAL_BITS))
m2_next_state <= m2_hold_clk_l;
else m2_next_state <= m2_gather;
slutt
m2_verify:
begynne
if (packet_good) m2_next_state <= m2_use;
else m2_next_state <= m2_wait;
slutt
m2_use:
begynne
output_strobe <= 1;
m2_next_state <= m2_wait;
sluttm2_hold_clk_l:
begynne
ps2_clk_hi_z <= 0 / / Dette starter vaktbikkje timer!
if (watchdog_timer_done & & ~ clean_clk) m2_next_state <= m2_data_low_1;
else m2_next_state <= m2_hold_clk_l;
slutt
m2_data_low_1:
begynne
ps2_data_hi_z <= 0 / / Skjemaer start bit, d [0] og d [1]
if (rising_edge & & (bit_count == 3))
m2_next_state <= m2_data_high_1;
else m2_next_state <= m2_data_low_1;
slutt
m2_data_high_1:
begynne
ps2_data_hi_z <= 1 / / Skjemaer d [2]
if (rising_edge & & (bit_count == 4))
m2_next_state <= m2_data_low_2;
else m2_next_state <= m2_data_high_1;
slutt
m2_data_low_2:
begynne
ps2_data_hi_z <= 0 / / Skjemaer d [3]
if (rising_edge & & (bit_count == 5))
m2_next_state <= m2_data_high_2;
else m2_next_state <= m2_data_low_2;
slutt
m2_data_high_2:
begynne
ps2_data_hi_z <= 1 / / Skjemaer d [4], d [5], d [6], d [7]
if (rising_edge & & (bit_count == 9))
m2_next_state <= m2_data_low_3;
else m2_next_state <= m2_data_high_2;
slutt
m2_data_low_3:
begynne
ps2_data_hi_z <= 0 / / Skjemaer paritetsbit
if (rising_edge) m2_next_state <= m2_data_high_3;
else m2_next_state <= m2_data_low_3;
slutt
m2_data_high_3:
begynne
ps2_data_hi_z <= 1 / / Allow musen til å dra lav (ACK puls)
if (falling_edge & & ps2_data) m2_next_state <= m2_error_no_ack;
else if (falling_edge & & ~ ps2_data)
m2_next_state <= m2_await_response;
else m2_next_state <= m2_data_high_3;
slutt
m2_error_no_ack:
begynne
error_no_ack <= 1;
m2_next_state <= m2_error_no_ack;
slutt
m2_await_response:
begynne
if (bit_count == 22) m2_next_state <= m2_verify;
else m2_next_state <= m2_await_response;
slutt
default: m2_next_state <= m2_wait;
endcase
slutt/ / State register
alltid @ (posedge clk)
begin: m3_state_register
if (reset) m3_state <= m3_data_ready_ack;
else m3_state <= m3_next_state;
slutt
/ / State overgang logikk
alltid @ (m3_state eller output_strobe eller lest)
begin: m3_state_logic
case (m3_state)
m3_data_ready_ack:
begynne
data_ready <= 1'b0;
if (output_strobe) m3_next_state <= m3_data_ready;
else m3_next_state <= m3_data_ready_ack;
slutt
m3_data_ready:
begynne
data_ready <= 1'b1;
if (les) m3_next_state <= m3_data_ready_ack;
else m3_next_state <= m3_data_ready;
slutt
default: m3_next_state <= m3_data_ready_ack;
endcase
slutt
/ / Dette er litt counter
alltid @ (posedge clk)
begynne
if (reset) bit_count <= 0 / / normal reset
else if (falling_edge) bit_count <= bit_count 1;
else if (watchdog_timer_done) bit_count <= 0; / / RX vaktbikkje timer reset
slutt
/ / Dette er skiftet register
alltid @ (posedge clk)
begynne
if (reset) q <= 0;
else if (falling_edge) q <= (ps2_data, q [ `TOTAL_BITS-1: 1]);
slutt
/ / Dette er vaktbikkje timer counter
/ / The watchdog timeren er alltid "aktivert" å bruke.
alltid @ (posedge clk)
begynne
if (reset | | rising_edge | | falling_edge) watchdog_timer_count <= 0;
else if (~ watchdog_timer_done)
watchdog_timer_count <= watchdog_timer_count 1;
slutt
tildele watchdog_timer_done = (watchdog_timer_count == WATCHDOG_TIMER_VALUE_PP-1);
/ / Dette er debounce timer counter
alltid @ (posedge clk)
begynne
if (reset | | falling_edge | | rising_edge) debounce_timer_count <= 0;
/ / Else if (~ debounce_timer_done)
else debounce_timer_count <= debounce_timer_count 1;
slutt
tildele debounce_timer_done = (debounce_timer_count == DEBOUNCE_TIMER_VALUE_PP-1);
/ / Dette er logikk for å bekrefte at en mottatte datapakke er "gyldig"
/ / Eller bra.
tildele packet_good = (
(q [0] == 0)
& & (Q [10] == 1)
& & (Q [11] == 0)
& & (Q [21] == 1)
& & (Q [22] == 0)
& & (Q [32] == 1)
& & (Q [9] == ~ ^ q [8:1]) / / odd parity bit
& & (Q [20] == ~ ^ q [19:12]) / / odd parity bit
& & (Q [31] == ~ ^ q [30:23]) / / odd parity bit
);
/ / Output spesielle skanne koden flagg, de skanner koden og ASCII
alltid @ (posedge clk)
begynne
if (reset)
begynne
left_button <= 0;
right_button <= 0;
x_increment <= 0;
y_increment <= 0;
slutt
else if (output_strobe)
begynne
left_button <= q [1];
right_button <= q [2];
x_increment <= (q [5], q [19:12]);
y_increment <= (q [6], q [30:23]);
slutt
sluttendmodule
/ / `undefine TOTAL_BITS
Jeg hjelper en kode for mus grensesnitt, men det fortsatt ikke fungerer.Kan noen hjelpe meg å sortere det ut?
`tidsskalaen 1ns / 1ps
////////////////////////////////////////////////// //////////////////////////////
/ / Firma:
/ / Engineer:
/ /
/ / Create Date: 19:54:03 04/20/06
/ / Design Navn:
/ / Module Name: dgfd
/ / Project Name:
/ / Målenheten:
/ / Tool versjoner:
/ / Description:
/ /
/ / Avhengigheter:
/ /
/ / Revisjon:
/ / Versjon 0.01 - Arkiv Opprettet
/ / Additional Comments:
/ /
////////////////////////////////////////////////// //////////////////////////////
`resetall
`tidsskala 1ns/100ps
`definere TOTAL_BITS 33 / / Antall bits i en full pakkemodul ps2_mouse_interface (
CLK,
reset,
ps2_clk,
ps2_data,
left_button,
right_button,
x_increment,
y_increment,
data_ready, / / rx_read_o
lese, / / rx_read_ack_i
error_no_ack
);
/ / Parameters
/ / Tidtakeren Verdien kan bli opp til (2 ^ bits) inkluderende.
parameter WATCHDOG_TIMER_VALUE_PP = 19660; / / Antall sys_clks for 400usec.
parameter WATCHDOG_TIMER_BITS_PP = 15; / / Antall bits trengs for tidtaker
parameter DEBOUNCE_TIMER_VALUE_PP = 186; / / Antall sys_clks for debounce
parameter DEBOUNCE_TIMER_BITS_PP = 8; / / Antall bits trengs for tidtakerparameter m1_clk_h = 0;
parameter m1_falling_edge = 1;
parameter m1_falling_wait = 3;
parameter m1_clk_l = 2;
parameter m1_rising_edge = 6;
parameter m1_rising_wait = 4;
parameter m2_reset = 14;
parameter m2_wait = 0;
parameter m2_gather = 1;
parameter m2_verify = 3;
parameter m2_use = 2;
parameter m2_hold_clk_l = 6;
parameter m2_data_low_1 = 4;
parameter m2_data_high_1 = 5;
parameter m2_data_low_2 = 7;
parameter m2_data_high_2 = 8;
parameter m2_data_low_3 = 9;
parameter m2_data_high_3 = 11;
parameter m2_error_no_ack = 15;
parameter m2_await_response = 10;
parameter m3_data_ready = 1;
parameter m3_data_ready_ack = 0;
/ / I / O erklæringer
input clk;
input reset;
Inout ps2_clk;
Inout ps2_data;
output left_button;
output right_button;
output [8:0] x_increment;
output [8:0] y_increment;
output data_ready;
input les;
output error_no_ack;
reg left_button;
reg right_button;
reg [8:0] x_increment;
reg [8:0] y_increment;
reg data_ready;
reg error_no_ack;
/ / Intern signal erklæringer
wire watchdog_timer_done;
wire debounce_timer_done;
wire packet_good;
reg [ `TOTAL_BITS-1: 0] q; / / Shift register
reg [2:0] m1_state;
reg [2:0] m1_next_state;
reg [3:0] m2_state;
reg [3:0] m2_next_state;
reg m3_state;
reg m3_next_state;
reg [5:0] bit_count; / / Bit counter
reg [WATCHDOG_TIMER_BITS_PP-1: 0] watchdog_timer_count;
reg [DEBOUNCE_TIMER_BITS_PP-1: 0] debounce_timer_count;
reg ps2_clk_hi_z; / / Uten tastatur, lik høy Z 1 skyldes pullups.
reg ps2_data_hi_z; / / Uten tastatur, lik høy Z 1 skyldes pullups.
reg clean_clk; / Debounced utgang fra M1, følger ps2_clk.
reg rising_edge; / / Output fra M1 stat maskin.
reg falling_edge; / / Output fra M1 stat maskin.
reg output_strobe; / Latches data data i produksjon registre
//------------------------------------------------ --------------------------
/ / Module kode
tildele ps2_clk = ps2_clk_hi_z? 1'bZ: 1'b0;
tildele ps2_data = ps2_data_hi_z? 1'bZ: 1'b0;
/ / State register
alltid @ (posedge clk)
begin: m1_state_register
if (reset) m1_state <= m1_clk_h;
else m1_state <= m1_next_state;
slutt
/ / State overgang logikk
alltid @ (m1_state
eller ps2_clk
eller debounce_timer_done
eller watchdog_timer_done
)
begin: m1_state_logic
/ / Output signaler standard til denne verdien, hvis ikke endres i en stat tilstand.
clean_clk <= 0;
rising_edge <= 0;
falling_edge <= 0;
case (m1_state)
m1_clk_h:
begynne
clean_clk <= 1;
if (~ ps2_clk) m1_next_state <= m1_falling_edge;
else m1_next_state <= m1_clk_h;
slutt
m1_falling_edge:
begynne
falling_edge <= 1;
m1_next_state <= m1_falling_wait;
slutt
m1_falling_wait:
begynne
if (debounce_timer_done) m1_next_state <= m1_clk_l;
else m1_next_state <= m1_falling_wait;
slutt
m1_clk_l:
begynne
if (ps2_clk) m1_next_state <= m1_rising_edge;
else m1_next_state <= m1_clk_l;
slutt
m1_rising_edge:
begynne
rising_edge <= 1;
m1_next_state <= m1_rising_wait;
slutt
m1_rising_wait:
begynne
clean_clk <= 1;
if (debounce_timer_done) m1_next_state <= m1_clk_h;
else m1_next_state <= m1_rising_wait;
slutt
default: m1_next_state <= m1_clk_h;
endcase
slutt/ / State register
alltid @ (posedge clk)
begin: m2_state_register
if (reset) m2_state <= m2_reset;
else m2_state <= m2_next_state;
slutt
/ / State overgang logikk
alltid @ (m2_state
eller q
eller falling_edge
eller rising_edge
eller watchdog_timer_done
eller bit_count
eller packet_good
eller ps2_data
eller clean_clk
)
begin: m2_state_logic
/ / Output signaler standard til denne verdien, hvis ikke endres i en stat tilstand.
ps2_clk_hi_z <= 1;
ps2_data_hi_z <= 1;
error_no_ack <= 0;
output_strobe <= 0;
case (m2_state)
m2_reset: / / Etter reset, sender kommandoen til musen.
begynne
m2_next_state <= m2_hold_clk_l;
slutt
m2_wait:
begynne
if (falling_edge) m2_next_state <= m2_gather;
else m2_next_state <= m2_wait;
slutt
m2_gather:
begynne
if (watchdog_timer_done & & (bit_count == `TOTAL_BITS))
m2_next_state <= m2_verify;
else if (watchdog_timer_done & & (bit_count < `TOTAL_BITS))
m2_next_state <= m2_hold_clk_l;
else m2_next_state <= m2_gather;
slutt
m2_verify:
begynne
if (packet_good) m2_next_state <= m2_use;
else m2_next_state <= m2_wait;
slutt
m2_use:
begynne
output_strobe <= 1;
m2_next_state <= m2_wait;
sluttm2_hold_clk_l:
begynne
ps2_clk_hi_z <= 0 / / Dette starter vaktbikkje timer!
if (watchdog_timer_done & & ~ clean_clk) m2_next_state <= m2_data_low_1;
else m2_next_state <= m2_hold_clk_l;
slutt
m2_data_low_1:
begynne
ps2_data_hi_z <= 0 / / Skjemaer start bit, d [0] og d [1]
if (rising_edge & & (bit_count == 3))
m2_next_state <= m2_data_high_1;
else m2_next_state <= m2_data_low_1;
slutt
m2_data_high_1:
begynne
ps2_data_hi_z <= 1 / / Skjemaer d [2]
if (rising_edge & & (bit_count == 4))
m2_next_state <= m2_data_low_2;
else m2_next_state <= m2_data_high_1;
slutt
m2_data_low_2:
begynne
ps2_data_hi_z <= 0 / / Skjemaer d [3]
if (rising_edge & & (bit_count == 5))
m2_next_state <= m2_data_high_2;
else m2_next_state <= m2_data_low_2;
slutt
m2_data_high_2:
begynne
ps2_data_hi_z <= 1 / / Skjemaer d [4], d [5], d [6], d [7]
if (rising_edge & & (bit_count == 9))
m2_next_state <= m2_data_low_3;
else m2_next_state <= m2_data_high_2;
slutt
m2_data_low_3:
begynne
ps2_data_hi_z <= 0 / / Skjemaer paritetsbit
if (rising_edge) m2_next_state <= m2_data_high_3;
else m2_next_state <= m2_data_low_3;
slutt
m2_data_high_3:
begynne
ps2_data_hi_z <= 1 / / Allow musen til å dra lav (ACK puls)
if (falling_edge & & ps2_data) m2_next_state <= m2_error_no_ack;
else if (falling_edge & & ~ ps2_data)
m2_next_state <= m2_await_response;
else m2_next_state <= m2_data_high_3;
slutt
m2_error_no_ack:
begynne
error_no_ack <= 1;
m2_next_state <= m2_error_no_ack;
slutt
m2_await_response:
begynne
if (bit_count == 22) m2_next_state <= m2_verify;
else m2_next_state <= m2_await_response;
slutt
default: m2_next_state <= m2_wait;
endcase
slutt/ / State register
alltid @ (posedge clk)
begin: m3_state_register
if (reset) m3_state <= m3_data_ready_ack;
else m3_state <= m3_next_state;
slutt
/ / State overgang logikk
alltid @ (m3_state eller output_strobe eller lest)
begin: m3_state_logic
case (m3_state)
m3_data_ready_ack:
begynne
data_ready <= 1'b0;
if (output_strobe) m3_next_state <= m3_data_ready;
else m3_next_state <= m3_data_ready_ack;
slutt
m3_data_ready:
begynne
data_ready <= 1'b1;
if (les) m3_next_state <= m3_data_ready_ack;
else m3_next_state <= m3_data_ready;
slutt
default: m3_next_state <= m3_data_ready_ack;
endcase
slutt
/ / Dette er litt counter
alltid @ (posedge clk)
begynne
if (reset) bit_count <= 0 / / normal reset
else if (falling_edge) bit_count <= bit_count 1;
else if (watchdog_timer_done) bit_count <= 0; / / RX vaktbikkje timer reset
slutt
/ / Dette er skiftet register
alltid @ (posedge clk)
begynne
if (reset) q <= 0;
else if (falling_edge) q <= (ps2_data, q [ `TOTAL_BITS-1: 1]);
slutt
/ / Dette er vaktbikkje timer counter
/ / The watchdog timeren er alltid "aktivert" å bruke.
alltid @ (posedge clk)
begynne
if (reset | | rising_edge | | falling_edge) watchdog_timer_count <= 0;
else if (~ watchdog_timer_done)
watchdog_timer_count <= watchdog_timer_count 1;
slutt
tildele watchdog_timer_done = (watchdog_timer_count == WATCHDOG_TIMER_VALUE_PP-1);
/ / Dette er debounce timer counter
alltid @ (posedge clk)
begynne
if (reset | | falling_edge | | rising_edge) debounce_timer_count <= 0;
/ / Else if (~ debounce_timer_done)
else debounce_timer_count <= debounce_timer_count 1;
slutt
tildele debounce_timer_done = (debounce_timer_count == DEBOUNCE_TIMER_VALUE_PP-1);
/ / Dette er logikk for å bekrefte at en mottatte datapakke er "gyldig"
/ / Eller bra.
tildele packet_good = (
(q [0] == 0)
& & (Q [10] == 1)
& & (Q [11] == 0)
& & (Q [21] == 1)
& & (Q [22] == 0)
& & (Q [32] == 1)
& & (Q [9] == ~ ^ q [8:1]) / / odd parity bit
& & (Q [20] == ~ ^ q [19:12]) / / odd parity bit
& & (Q [31] == ~ ^ q [30:23]) / / odd parity bit
);
/ / Output spesielle skanne koden flagg, de skanner koden og ASCII
alltid @ (posedge clk)
begynne
if (reset)
begynne
left_button <= 0;
right_button <= 0;
x_increment <= 0;
y_increment <= 0;
slutt
else if (output_strobe)
begynne
left_button <= q [1];
right_button <= q [2];
x_increment <= (q [5], q [19:12]);
y_increment <= (q [6], q [30:23]);
slutt
sluttendmodule
/ / `undefine TOTAL_BITS