Trenger noen tips om å få pixel data fra minnet på FPGA

W

win3y

Guest
Hei, alle sammen!
Jeg vet ikke hvordan du kode en modul som har funksjon for å få pixel data som gjeldende piksel og referanse pixel fra memomy for beregning bevegelse estimering.Pls gi meg noen råd å implementere det.For eksempel er effekten av ovenstående modul pixel data som synkroniseres ved klokken Pusle inngang.
Mange takk.

 
Velg FPGA du planlegger å bruke så se på brukerne for detaljer om hvordan å implementere ombord minne.

E

 
Du kan sende gjeldende pixel eller referanse piksel.
Detials finnes i papir
KM Yang, MT Sun, og L. Wu, "A Family of VLSI Design for Motion Compensation Block-matchende Algorithm," IEEE Transactions on Circuits and Systems, ss.1317-1325, 1989 oktober

Liang-Gee Chen's team leder variabel blokkstørrelse ME forskning nå.En oppsummering av mange typer ME arkitektur er i hans avis: Analyse og arkitektur design av variabel block-størrelsen motion estimation for H.264/AVCLagt etter 4 minutter:Jeg har implementere noen arhitectures for FPGA er dataflyt kontrollere bigest challange, spesielt for store Vidoe størrelse.

 
nxtech skrev:

Velg FPGA du planlegger å bruke så se på brukerne for detaljer om hvordan å implementere ombord minne.E
 
HI WIN3Y
første hvordan du lagrer du data i minnet?. blokk ram på FPGA eller du bruker ekstern ram? og da vil du designe output modul?
hvorfor ikke du fortelle clearlt om programmets wrorking Kanskje jeg kan hjelpe deg.
lykke til!

 
Kanskje trenger du å bygge en addr generator å pumpe både Y-data for gjeldende pix og referanse pix form Deferent minner.Den addr er sammensatt med base addr og offset Adr.Basen addr definerer MB posisjon i pic, og offset addr skanner Y dataene i MB.De ulike referanse addrs finnes i PE array.
Jeg tror Søn MT's paper diskuterte Adr generator tydelig.

 
til darui:

Hvilken oppløsning er det du får og hva FPGA enheter som du brukte for det oppløsning?

 
darui skrev:

Kanskje trenger du å bygge en addr generator å pumpe både Y-data for gjeldende pix og referanse pix form Deferent minner.
Den addr er sammensatt med base addr og offset Adr.
Basen addr definerer MB posisjon i pic, og offset addr skanner Y dataene i MB.
De ulike referanse addrs finnes i PE array.

Jeg tror Søn MT's paper diskuterte Adr generator tydelig.
 
Jeg brukte primitive fordi det kan sette verdien for DCT Quant ved hjelp kanten av toporters minne.u kan også bruke CoreGenerator men flere filer er generert.
Den flyter er en modul til en toporters RAM jeg brukte for Vidoe data acqusition.Jeg brukte 8 Bram av denne typen for å formatere BT656 til MB basert.

modul sv_zsram00 (DOA, DOB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, ENA, ENB, WEA, WEB);

output [1] DOA; / / 32-bit A port data output
output [15] DOB; / / 32-bits B port data output
/ /. DOPA (DOPA), / / 4-bits A port paritet data output
/ /. DOPB (DOPB), / / 4-bits B port paritet data output
input [12] ADDRA; / / 15-bit A portadressen inngang
input [9] ADDRB; / / 15-bits B portadressen inngang
/ /. CASCADEINA (CASCADEINA), / / 1-bit cascade A inngang
/ /. CASCADEINB (CASCADEINB), / / 1-bit cascade B-inngang
input CLKA; / 1-bit A port klokke inngang
input CLKB; / 1-bit B port clock input
input [1] DIA; / / 32-bit A port data input
input [15] DIB; / / 32-bits B port data input
/ /. DIPA (DIPA), / / 4-bits A port paritet data input
/ /. DIPB (DIPB), / / 4-bits B port paritet data input
input ENA / / 1-bit A port aktivere input
input ENB; / 1-bit B port aktivere input
/ /. REGCEA (REGCEA), / / 1-bit A port register aktivere input
/ /. REGCEB (REGCEB), / / 1-bit B port register aktivere input
/ /. SSRA (SSRA), / / 1-bit A port set / reset inngang
/ /. SSRB (SSRB), / / 1-bit B port set / reset inngang
input WEA; / 4-bits A port skriver aktivere input
input WEB; / 4-bits B-port skriver aktivere input

RAMB16_S2_S18 # (
/ /. DOA_REG (1), / / Optional utgang registrerer på A-port (0 eller 1)
/ /. DOB_REG (1), / / Optional utgang registrerer på B-port (0 eller 1)
. INIT_A (36'h000000000) / / Initial verdiene på A-utgang
. INIT_B (36'h000000000) / / Initial verdiene på B-utgang
/ /. INVERT_CLK_DOA_REG ( "false"), / / Inverter klokke på en port utgang registre ( "true" eller "false")
/ /. INVERT_CLK_DOB_REG ( "false"), / / Inverter klokke på en port utgang registre ( "true" eller "false")
/ /. RAM_EXTENSION_A ( "none"), / / "ØVRE", "NEDRE" eller "ingen" når cascaded
/ /. RAM_EXTENSION_B ( "none"), / / "ØVRE", "NEDRE" eller "ingen" når cascaded
/ /. READ_WIDTH_A (9), / / Gyldige verdier er 1, 2, 4, 9, 18, eller 36
/ /. READ_WIDTH_B (1

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Kjølig" border="0" />

, / / Gyldige verdier er 1, 2, 4, 9, 18, eller 36
/ /. SIM_COLLISION_CHECK ( "ALLE"), / / Collision sjekk aktivere "ALLE", "WARNING_ONLY",
/ / "GENERATE_X_ONLY" eller "ingen"
. SRVAL_A (36'h000000000), / / Set / Reset verdi for en port utgang
. SRVAL_B (36'h000000000), / / Set / Reset verdi for B-port utgang
. WRITE_MODE_A ( "READ_FIRST"), / / "WRITE_FIRST", "READ_FIRST", eller "no_change"
. WRITE_MODE_B ( "READ_FIRST"), / / "WRITE_FIRST", "READ_FIRST", eller "no_change"
/ /. WRITE_WIDTH_A (9), / / Gyldige verdier er 1, 2, 4, 9, 18, eller 36
/ /. WRITE_WIDTH_B (1

<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Kjølig" border="0" />

, / / Gyldige verdier er 1, 2, 4, 9, 18, eller 36

/ / Følgende INIT_xx erklæringene angi den opprinnelige innholdet i RAM
. INIT_00 (256'h8ffa49fae1e52c4b8f8f8f8f4be52c4b8f8f8f462be14b4b8f8f4949f1fae8fa)
. INIT_01 (256'h8f8f49fb493bfbe58f8ffbfb493bfb13fa8f8f492c2c2c13fa498f462c2c2c13)
. INIT_02 (256'h96a5bdc9c4b18f798995a4afb29f8672717b8795938373616069737e7d726559)
. INIT_03 (256'h4b61819b9c886b58607591acab9577617d9075c0bda5826b90a2bacfc9af8d77)
. INIT_04 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_05 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_06 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_07 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_08 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_09 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_0A (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_0B (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_0C (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_0D (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_0E (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_0F (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_10 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_11 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_12 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_13 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_14 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_15 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_16 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_17 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_18 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_19 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_1A (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_1B (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_1C (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_1D (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_1E (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_1F (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_20 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_21 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_22 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_23 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_24 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_25 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_26 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_27 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_28 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_29 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_2A (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_2B (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_2C (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_2D (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_2E (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_2F (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_30 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_31 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_32 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_33 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_34 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_35 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_36 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_37 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_38 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_39 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_3A (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_3B (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_3C (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_3D (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_3E (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INIT_3F (256'h05a805a805a805a805a805a805a805a800000000000000000000000000000000)

/ / Det neste settet med INITP_xx er for parity bits
. INITP_00 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INITP_01 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INITP_02 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INITP_03 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INITP_04 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INITP_05 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INITP_06 (256'h0000000000000000000000000000000000000000000000000000000000000000)
. INITP_07 (256'h0000000000000000000000000000000000000000000000000000000000000000)
) RAMB16_inst (
/ /. CASCADEOUTA (CASCADEOUTA), / / 1-bit kaskade utgang
/ /. CASCADEOUTB (CASCADEOUTB), / / 1-bit kaskade utgang
. DOA (DOA), / / 32-bit A port data output
. DOB (DOB), / / 32-bits B port data output
/ /. DOPA (DOPA), / / 4-bits A port paritet data output
/ /. DOPB (DOPB), / / 4-bits B port paritet data output
. ADDRA (ADDRA), / / 15-bit A portadressen inngang
. ADDRB (ADDRB), / / 15-bits B portadressen inngang
/ /. CASCADEINA (CASCADEINA), / / 1-bit cascade A inngang
/ /. CASCADEINB (CASCADEINB), / / 1-bit cascade B-inngang
. CLKA (CLKA), / / 1-bit A port klokke inngang
. CLKB (CLKB), / / 1-bit B port clock input
. DIA (DIA), / / 32-bit A port data input
. DIB (DIB), / / 32-bits B port data input
/ /. DIPA (DIPA), / / 4-bits A port paritet data input
/ /. DIPB (DIPB), / / 4-bits B port paritet data input
. ENA (ENA), / / 1-bit A port aktivere input
. ENB (ENB), / / 1-bit B port aktivere input
/ /. REGCEA (1'b0), / / 1-bit A port register aktivere input
/ /. REGCEB (1'b0), / / 1-bit B port register aktivere input
. SSRA (1'b0), / / 1-bit A port set / reset inngang
. SSRB (1'b0), / / 1-bit B port set / reset inngang
. WEA (WEA), / / 4-bits A port skriver aktivere input
. WEB (WEB) / / 4-bits B-port skriver aktivere input
);

endmoduleLagt etter 3 minutter:følgende er en enkel testbench

`tidsskalaen 1ns / 1ps

////////////////////////////////////////////////// //////////////////////////////
/ / Firma:
/ / Engineer:
/ /
/ / Create Date: 20:57:46 11/22/2005
/ / Design Navn: sv_sram_dct_primitive
/ / Module Name: sim_sram.v
/ / Project Name: SV_TEST1
/ / Målenheten:
/ / Tool versjoner:
/ / Description:
/ /
/ / Verilog Test Armatur opprettet av ISE for modulen: sv_sram_dct_primitive
/ /
/ / Avhengigheter:
/ /
/ / Revisjon:
/ / Versjon 0.01 - Arkiv Opprettet
/ / Additional Comments:
/ /
////////////////////////////////////////////////// //////////////////////////////

module sim_sram_v;

/ / Inputs
reg [12:0] ADDRA;
reg [9:0] ADDRB;
reg CLKA;
reg CLKB;
reg [1:0] DIA;
reg [9:0] DIB;
reg ENA;
reg ENB;
reg WEA;
reg WEB;

/ / Outputs
wire [1:0] DOA;
wire [15:0] DOB;
wire [3:0] off_portb;
tildele off_portb = 4'b1111;

/ / Instantiate biomaterialer Under Test (Uut)
/ / sv_sram_dct_primitive Uut (
sv_zsram00 Uut (
. DOA (DOA),
. DOB (DOB)
. ADDRA (ADDRA)
. ADDRB (ADDRB [9:0 ]),//{ off_portb [3:0], ADDRB [5:0]))
. CLKA (CLKA)
. CLKB (CLKB)
. DIA (DIA),
. DIB (DIB),
. ENA (ENA),
. ENB (ENB)
. WEA (WEA)
. WEB (WEB)
);

wire [47:0] p_out;
wire [15:0] data_doa;
/ / Tildele data_doa = (DOA [7:7], DOA [7:7], DOA [7:7], DOA [7:7], DOA [7:7], DOA [7:7], DOA [ 7:7], DOA [7:7], DOA [7:0]);
reg RST;
/ * DspSet_dct uut_dct (
. CLK (CLKA)
. cs (ADDRA [2:0]),
. RST (RST)
. data_doa (data_doa)
. p_out (p_out)
); * /

reg [7:0] i;

innledende begynne
/ / Initialize Inputs
ADDRA = 0;
ADDRB = 0;
CLKA = 1;
CLKB = 1;
DIA = 0;
DIB = 0;
ENA = 1;
ENB = 1;
WEA = 0;
WEB = 1;
RST = 0;
# 103 RST = 1;

/ / Vent 100 ns for global tilbakestilling til slutt
# 100;
ENA = 1;
ENB = 1;
for (i = 0; i <64; i = i 1)
begynne
# 20
ADDRA = i;
ADDRB = i;
slutt
# 100;
$ stopp;

/ / Add stimulans her

slutt

alltid # 10 CLKA = ~ CLKA;
alltid # 10 CLKB = ~ CLKB;

endmodule

 
WOW, det er virkelig fantastisk!Jeg gjør det nå, takk så mye!
Hvis jeg har noen spørsmål, pls hjelpe meg igjen

<img src="http://www.edaboard.com/images/smiles/icon_biggrin.gif" alt="Very Happy" border="0" />Have nice day!

 
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